1.1phy控制器和DDR颗粒上电 1.2 复位DDR颗粒 1.3 CKE使能和ck_t/ck_c打开 1.4 MRS寄存器模式...
将模板中 Memory interface ports 和 System Clock Ports 的端口作为 ddr3_motive 的模块端口,其中 init_calib_complete 信号被我删除了,主要是考虑到本次只是将init_calib_complete 信号拉起,没有考虑用户逻辑,所以在内部引出来就可以了。还有一个地方需要注意的就是 IP 生成的时候,系统时钟采用的是 No Buffer ...
But somehow, the init_calib_complete always stays low and as the calibration is not over, I guess I do not get to perform read and write to the memory. The dq always stays into high impedence state. Is there anything I can do differently? I am using ddr3.v file and using ...
SIM_BYPASS_INIT_CAL : string := "FAST"; -- # = "OFF" - Complete memory init & -- calibration sequence -- # = "SKIP" - Not supported -- # = "FAST" - Complete memory init & use -- abbreviated calib sequence SIMULATION : string := "TRUE"; -- Should be TRUE during design sim...
除了UCF以外，没有加我自己的东西，完全是mig生成的工程 仿真没有问题但是debug时init calib complete没...
I created a DDR interface for KC705 using the XTP196 (KC705 MIG Design Creation) document and then I generted the MIG example design . I used Vivado simulator to simulate the exmple design and I can see the init_calib_complete is '0'. It seems the calibration process does not finish ...