That syntax is called anindexed part-select. The first term is the bit offset and the second term is the width. It allows you to specify a variable for the offset, but the width must be constant. Example from the SystemVerilog 2012 LRM: logic [31:0] a_vect; logic [0:31] b_vect;...
); // We can't part-select multiple bits without an error, but we can select one bit at a time, // four times, then concatenate them together. assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]}; // Alternatively, "indexed vector part select" works bet...
This is where the new port attributepli_access()comes to our help.pli_access() allows you to access the HDL object, in this case the SV or Verilog array, with the PLI -- which is the C interface of the simulator -- rather than through stub access. Let's look at an example which ...
That syntax is called anindexed part-select. The first term is the bit offset and the second term is the width. It allows you to specify a variable for the offset, but the width must be constant. Example from the SystemVerilog 2012 LRM: logic[31: 0]a_vect;logic[0 :31]b_vect;logic...