That syntax is called anindexed part-select. The first term is the bit offset and the second term is the width. It allows you to specify a variable for the offset, but the width must be constant. Example from the SystemVerilog 2012 LRM: logic [31:0] a_vect; logic [0:31] b_vect;...
That syntax is called anindexed part-select. The first term is the bit offset and the second term is the width. It allows you to specify a variable for the offset, but the width must be constant. Example from the SystemVerilog 2012 LRM: logic[31: 0]a_vect;logic[0 :31]b_vect;logic...
Please note that pli_access() can be used to access only static arrays which are not defined inside classes. pli_access() also eliminates the need to create a stub file when using the part select on a signal's hdl_path() when using the VCS simulator. Please refer todocumentationfor more...