All optical NAND gateAll optical half adderThe computation of digital combinational and sequential logic functionality in the optical domain is one of the most important aspects, which opens the door of fast, s
In this paper, the first demonstration of a programmable double-output optical threshold logic gate is presented via an optoelectronic circuit. Some basic fuzzy logic implementations are also proposed by employing these optoelectronic circuits. AND, OR, NAND, NOR, MAJORITY, MINORITY are demonstrated ...
1a). The fabricated 3D FeNAND had three layers, and eight memory cells were positioned at each layer (Fig. 1b, c). The device structure and thickness of each layer were confirmed using transmission electron microscopy (TEM). The thickness of the TiN gate electrode and the width of the ...
There are many reversible universal quantum logic gates such as the CNOT, Fredkin gate and Toffoli gate amongst others. The reversible quantum logic gates have a one to one mapping of the inputs and outputs and also have many advantages, such as less heat generation, no loss of information,...
MZI can play a significant role in this field of ultra-fast all-optical signal processing [6], [7], [8]. The performance of SOA-MZI-based XOR gate have been analyzed through numerical simulations, to generalize the optimal parameters as well as the suitable operating conditions [9], [10...
During the standardisation process of post-quantum cryptography, NIST encourages research on side-channel analysis for candidate schemes. As the recommended lattice signature scheme, CRYSTALS-Dilithium, when implemented on hardware, has seen limited rese
[kGE/MHz] [24] 130 nm 64-QAM MBF-FD tabular no 350 198 1.77 [11] 250 nm 16-QAM STS-SD SE no 56.8 137b 0.41 This work 130 nm BPSK to 64-QAM STS-SD ordered ∞-norm no 3× 70.4 97.1 183 383 0.38 0.25 aOne GE corresponds to the area of a two-input drive-one NAND gate....
∗Number of NAND gate equivalents. Table 6.Cache speed. Figure 12 Open in figure viewerPowerPoint 5× 5 mm2chip layout. Tables7and8show the evaluation result of the hardware scale overhead. The conventional cache adopts two-tag-banks structure for aligned/unaligned row-directional data access...
The majority gate can be used to generate an “AND” or an “OR” logic, by putting one of the inputs as “0” and “1,” respectively. Figure 3 Open in figure viewerPowerPoint Realization of logical OR and AND gates. The QCA clocking system synchronization is used for controlling ...
technology.TheTernaryNANDGateandTernaryNORGatearealsodesignedandsimulated.TheternarySRAMconsistsofcross- coupledternaryinverters.SPICEsimulationsconfirmedthatthefunctionalbehavioroftheREADandWRITEoperationsis correct. Keywords–Multiple-valuedlogic(MVL),CMOSTernaryLogic,TernarySRAM,SimpleTernaryInverter(STI),PositiveTernary...