All optical NAND gateAll optical half adderThe computation of digital combinational and sequential logic functionality in the optical domain is one of the most important aspects, which opens the door of fast, secure and efficient switching and communication activity in the modern technological scenario...
In this paper, the first demonstration of a programmable double-output optical threshold logic gate is presented via an optoelectronic circuit. Some basic fuzzy logic implementations are also proposed by employing these optoelectronic circuits. AND, OR, NAND, NOR, MAJORITY, MINORITY are demonstrated ...
technology.TheTernaryNANDGateandTernaryNORGatearealsodesignedandsimulated.TheternarySRAMconsistsofcross- coupledternaryinverters.SPICEsimulationsconfirmedthatthefunctionalbehavioroftheREADandWRITEoperationsis correct. Keywords–Multiple-valuedlogic(MVL),CMOSTernaryLogic,TernarySRAM,SimpleTernaryInverter(STI),PositiveTernary...
[kGE/MHz] [24] 130 nm 64-QAM MBF-FD tabular no 350 198 1.77 [11] 250 nm 16-QAM STS-SD SE no 56.8 137b 0.41 This work 130 nm BPSK to 64-QAM STS-SD ordered ∞-norm no 3× 70.4 97.1 183 383 0.38 0.25 aOne GE corresponds to the area of a two-input drive-one NAND gate....
This paper presents an optimized geometric greedy router (GGR) based on quantum dot cellular automata (QCA) technology. The proposed structure of GGR is based on a spanning tree of the network. This ...
(111) orthorhombic phase of HfZrOx45. The trench-based vertical structure of the proposed 3D FeNAND can lead to higher memory density compared to gate-all-around (GAA) structures. When similar device dimensions are considered, the trench-based vertical structure can achieve double memory density ...
History4 Commits ALU.v README.md Untitled.jpeg Repository files navigation README HackALU_Verilog My implementation of the HACK ALU described in the NAND2Tetris course, in Verilog. Used if_else statements instead of the MUX gate, and implemented the 2's complement system during negation.Ab...
A family of full-custom conventional CMOS Logic and an Adiabatic Logic units for example, an inverter, a two-input NAND gate, a two-input NOR gate, a two- input XOR gate a two-to-one multiplexer and a one- bit Full Adder were designed in Mentor Graphics IC Design Architect using ...
an address decoder coupled with said memory bank and said selector and operative to select said memory cell transistor and provide said selected voltage to said gate input; a read circuit operative to read the output of said selected memory cell transistor and whether said selected voltage is gre...
Multiresolution processing apparatus (which may be programmed as pyramid processing apparatus) comprised of a filter logic unit comprised of one or a plurality of identical interconnected programmable modules; a set of programmable multiplexers (MUX), a plurality of programmable random access-memories (...