Syntax Conditional compilation can be achieved with Verilog`ifdefand`ifndefkeywords. These keywords can appear anywhere in the design and can be nested one inside the other. The keyword`ifdefsimply tells the compiler to include the piece of code until the next`elseor`endifif the given macro call...
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The`ifdef,`else,`elsif,`endif, and`ifndef compiler directives have the syntax shown in Syntax 0-1.conditional_compilation_directive ::= ifdef_directive | ifndef_directive ifdef_directive ::= `ifdef text_macro_identifier ifdef_group_of_lines {`elsif text_macro_identifier elsif_group_of_lines }...