I believe Modelsim switched to this behavior even when compiling pure Verilog designs. Global defines are particularly troublesome for IP developers. A user can disable implicit net declarations with a compiler directive and thereby break the IP that relied on a perfectly legal (an...
—If there is an`elsif compiler directive,the elsif text macro identifier is tested to see if it is defined as a text macro name using`define within the Verilog HDL source description.—If the elsif text macro identifier is defined,the elsif group of lines is compiled as part ...