首先，assign hsync=(hcount>hsync_end)是Verilog HDL中的语句，不是VHDL中的语句。你对这个连续赋值语句的理解是对的，assign hsync=(hcount>hsync_end)描述的是hsync等于一个逻辑值（真=1，假=0），hcount>hsync_end成立时为真（=1），不成立时为假（=0）。
I'm afraid that the MIPI DSI interface is not designed to generate HSYNC/VSYNC end packets, only start pulses, as stated on the following application note that goes into detail on how the MIPI DSI and CSI work on our devices:i.MX 8/RT MIPI DSI/CSI-2 (nxp.com) ...
Hi guys, I have to set my display resolution with hdmi is 800x600, but i have no idea about some of paramters(hsync start, vsync start). So, I need