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您可以使用此IPhttps：//www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug...
0 Kudos Reply 03-16-2015 10:21 PM 9,246 Views qiang_li-mpu_se NXP Employee It seems the VSYNC and HSYNC is must in LDB side to convert the display signal to LVDS serial signal. Another thing can be tried is to switch the low/high active for HSYNC and VSYNC, the original...
错误信息:2019-10-30 11:07:49,400 ERROR [master/master:16000:becomeActiveMaster] master.HMaster: Failed to beco...
/* Setup active data waveform to sync with DC */ _ipu_di_sync_config(disp, 5, 0, DI_SYNC_HSYNC, v_sync_width + v_start_width, DI_SYNC_HSYNC, height, DI_SYNC_VSYNC, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); 2. Old: _ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK, h_...
Border : 0 Pixels Frequency : 70 kHz Vertical: Active Time : 1140 Lines Blanking Time : 30 Lines Sync Offset : 10 Lines Sync Pulse Width: 6 Lines Border : 0 Lines Digital Separate, Horizontal Polarity (+), Vertical Polarity (+)
/* Setup active data waveform to sync with DC */ _ipu_di_sync_config(ipu, disp, 4, 0, DI_SYNC_HSYNC, v_sync_width + v_start_width, DI_SYNC_HSYNC, height, DI_SYNC_VSYNC, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); _ipu_di_sync_config(ipu, d...
width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); with the code using the above defines: /* Setup active data waveform to sync with DC */ _ipu_di_sync_config(disp, DI_COUNTER_ALINE, 0, DI_SYNC_HSYNC, v_sync_width + v_start_width, DI_SYNC_H...