在读三星的那篇HBM-PIM的论文时,理了一下HBM的结构,它是一个伪通道(pCH)一次access给64bit数据,单层的die有两个通道4个伪通道,因此HBM的位宽是128×8或64×16 = 1024bit Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology, ISCA'21 文中给出了如图的HBM die结构,...
[3] Kim et al.A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM.ISCA 2012. [4] Lee et al.Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture.HPCA 2013. [5] Seshadri et al.RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization.MICRO...