All optical NAND gateAll optical half adderThe computation of digital combinational and sequential logic functionality in the optical domain is one of the most important aspects, which opens the door of fast, secure and efficient switching and communication activity in the modern technological scenario...
whereas half adder has only two inputs and two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. When a full-adder logic is designed, you string eight of them together to create a byte-wide adder and cascade the ...
Implementation of all-optical NAND logic gate and half adder using the micro-ring resonator structures. Opt Quant Electron 2016;48:477.10.1007/s11082-016-0747-zSearch in Google Scholar [49] Birr T, Zywietz U, Chhantyal P, Chichkov BN, Reinhardt C. Ultrafast surface plasmon-polariton logic ...
The all-optical NAND ga... SH Kim,JH Kim,BG Yu,... - IEEE 被引量: 137发表: 2005年 All-optical half adder using cross gain modulation in semiconductor optical amplifiers By using the gain nonlinearity characteristics of semiconductor optical amplifier, an all-optical binary half adder at 10...
In this paper, we perform a physical-information-theoretic analysis on the efficiency limitations in a Brownian NAND and half-adder circuits implemented using SET technology. The method we employed here establishes a solid ground that enables studying computational and physical features of this emerging...
half adder 10. The first half adder 10 includes a NOR gate 14 and a NAND gate 16 both of which are connected to receive an external data signal D1and a carry signal C1. The NOR gate 14 has an output connected to one input of another NOR gate 18, and the NAND gate 16 is ...
In this paper, an optical half adder is designed using photonic crystals. One of the features of this half adder is its small size. In the design of this structure, it has been tried to have a small size, shorter delay and high contrast ratio so that it can be used in the design of...
Amazawa, et al., “Fully Planarized Four-Level Interconnection with Stacked VLAS Using CMP of Selective CVD-A1 and Insulator and its Application to Quarter Micron Gate Array LSIs”, 1995, IEEE. Axelrad et al. “Efficient Fuoo-Chip Yield Analysis Methodology for OPC-Corrected VLSI Design”,...
Half Subtractor using NAND Gates - In digital electronics, a subtractor is a combinational logic circuit that performs the subtraction of two binary numbers. However, the subtraction of binary number can be performed using adder circuits by taking 1’s o
Full Adder Design with using NAND Gates A NAND gate is one kind of universal gate, used to execute any kind of logic design. The FA circuit with the NAND gates diagram is shown below. FA using NAND Gates FA is an easy one-bit adder and if we desire to execute the addition of n-bi...