whereas half adder has only two inputs and two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. When a full-adder logic is designed, you string eight of them together to create a byte-wide adder and cascade the ...
Design and implementation of all-optical half adder using cross gain modulation in semiconductor optical amplifiers By using only two input signals of A and B, an all-optical half adder that utilizes a cross gain modulation in semiconductor optical amplifiers is demonstr... JH Kim,CW Son,G Kim...
All optical NAND gateAll optical half adderThe computation of digital combinational and sequential logic functionality in the optical domain is one of the most important aspects, which opens the door of fast, secure and efficient switching and communication activity in the modern technological scenario...
In this paper, we perform a physical-information-theoretic analysis on the efficiency limitations in a Brownian NAND and half-adder circuits implemented using SET technology. The method we employed here establishes a solid ground that enables studying computational and physical features of this emerging...
As well known, NOR gates and NAND gates of the CMOS logic need four FETs, and NOT gates require two FETs in the CMOS logic. Therefore, the half adder shown in FIG. 1 needs 14 FETs per one bit. Thus, if a half adder of n bits is constructed, 14n FETs are required. For example...
In this paper, an optical half adder is designed using photonic crystals. One of the features of this half adder is its small size. In the design of this structure, it has been tried to have a small size, shorter delay and high contrast ratio so that it can be used in the design of...
The SEM image of the half-adder sample without the nano-Au:(IR140:MEH-PPV) nanocomposite cover layer is shown in Figure 1B. Finally, a 100-nm-thick nano-Au:(IR140:MEH-PPV) film was deposited onto the upper surface of the full-adder sample by using spin coating method, and the ...
A gate electrode level region above the substrate portion includes a number of conductive features that extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features ...
Half Subtractor using NAND Gates - In digital electronics, a subtractor is a combinational logic circuit that performs the subtraction of two binary numbers. However, the subtraction of binary number can be performed using adder circuits by taking 1’s o
Full Adder Design with using NAND Gates A NAND gate is one kind of universal gate, used to execute any kind of logic design. The FA circuit with the NAND gates diagram is shown below. FA using NAND Gates FA is an easy one-bit adder and if we desire to execute the addition of n-bi...