In the rare cases where the data received via GMII arrives on the Avalon-ST RX bus, it looks like this: This is it should always look like! Translate Labels Interface Protocol - Ethernet Tags: Avalon-ST data_rx_valid GMII gmii_rx_dv TSE 0 Kudos Reply Zarquin New...
data_rx_valid GMII gmii_rx_dv TSE 0 Kudos Reply Zarquin New Contributor II 10-07-2023 06:24 AM 1,210 Views Wasn't a timing problem. It was a evaluation dialogue window problem:community.intel.com/t5/FPGA-Intellectual-Property/Triple-Speed-Ethernet-MII-GMII-Timing-Issue/m-p...
data_rx_valid GMII gmii_rx_dv TSE 0 Kudos Reply Zarquin New Contributor II 10-07-2023 06:24 AM 1,219 Views Wasn't a timing problem. It was a evaluation dialogue window problem:community.intel.com/t5/FPGA-Intellectual-Property/Triple-Speed-Ethernet-MII-GMII-Timing-Issue/m-p/...
data_rx_valid GMII gmii_rx_dv TSE 0 Kudos Reply Zarquin New Contributor II 10-07-2023 06:24 AM 1,219 Views Wasn't a timing problem. It was a evaluation dialogue window problem:community.intel.com/t5/FPGA-Intellectual-Property/Triple-Speed-Ethernet-MII-GMII-Timing-Issue/m-p/...
In the rare cases where the data received via GMII arrives on the Avalon-ST RX bus, it looks like this: This is it should always look like! Translate Labels Interface Protocol - Ethernet Tags: Avalon-ST data_rx_valid GMII gmii_rx_dv TSE 0 Kudos Reply Zarquin New Contributor ...
data_rx_valid GMII gmii_rx_dv TSE 0 Kudos Reply Zarquin New Contributor II 10-07-2023 06:24 AM 1,213 Views Wasn't a timing problem. It was a evaluation dialogue window problem:community.intel.com/t5/FPGA-Intellectual-Property/Triple-Speed-Ethernet-MII-GMII-Timing-...