adder with minimum quantum cost and is simulated in xilinx 9.1i using verilog code delay in carry skip adder and carry look ahead adder is 27ns and 40 ns with power loss of 24 and 48 uW the quantum cost of CLA( carry look ahead adder) is 254 and 340 for CSA( carry skip ...
The 3脳3 "Modified QR Gate" (Reversible gate also) is also used to provide a new extra logical expression that is used for super-computing. In this also cited the logical design and validate by Verilog Code using Xilinx.doi:10.1007/978-981-15-7394-1_32Rupsa RoySwarup SarkarSourav Dhar...