Pre-Adder Dynamically Configured Followed by Multiplier and Post-Adder (Verilog) Pre-Adder Dynamically Configured Followed by Multiplier and Post-Adder (VHDL) Using the Squarer in the UltraScale DSP Block Square of a Difference (Verilog)
Get a RTL schematic using a toolchain like Vivado to find out what the inputs and outputs of the FPGA are used for (UART TX/RX, reset, clock). Code a testbench in Verilog to be able to communicate with the FPGA over UART and send/receive data -> it encrypts 8-byte blocks and se...