两者都运行无限的仿真时间,并且在它们内部有一个延迟元件很重要。forever An always or forever block without a delay element will hang in simulation! always// Single statementalwaysbegin// Multiple statementsend 在SystemVerilog中,block不能
In SystemVerilog, analwaysblock cannot be placed inside classes and other SystemVerilog procedural blocks. Instead we can use aforeverloop to achieve the same effect. The pseudo code shown below mimics the functionality of a monitor in testbench that is once started and allowed to run as long ...