My problem here is regarding on the testbench where it shows fatal error while loading at the end of the modelsim simulation. Precisely, the errors are about as follows: i)# ** Error: (vsim-3389) C:/Users/Rheeshaalaen/Desktop/sw_pe_affine/sw_gen_testbench.v(9...
# FATAL ERROR while loading design 用Modelsim 进行时序仿真时,一个错误搞抓狂:Fatal: SDF files require Altera primitive library找了一天终于知道了原因是工程使用了Altera的原语,需要altera仿真库支持。 比如我们选用器件cycloneii,需要找到相应的cycloneii_atom.v文件(路径:安装目录\quartus\eda\sim_lib)如果我们编...
The RTL simulation works OK but if I launch the gate level simulation the ModelSim reports:# ALTERA version supports only a single HDL# ** Fatal: (vsim-3039) D:/... failed.# FATAL ERROR while loading design# Error loading design# Error: Error loading design Can anybody help me? Man...
# FATAL ERROR while loading design To prevent this error, recompile the files using the newer version of Modelsim that you are using. You can also refresh the libraries compiled using previous version by using - refresh option of Modelsim's vlog command as shown below: ...
(errno = ERANGE) # # # FATAL ERROR while loading design # Error loading design Error loading design # End time: 11:13:04 on May 13,2024, Elapsed time: 0:00:02 # Errors: 1, Warnings: 0 make: *** [run_modelsim] 错误12 相关github repo: https://github.com/mitshine/tutorials-on...
While doing C/RTL co-simulation of example design (sc_sequ_cthread) for vhdl, Vivado HLS 2012.3 is able to generate the cosim.modelsim.scr script successfully. When this script is sourced with the command ``vsim -gui -do cosim.modelsim.scr``, the error message below is returned: ...
My problem here is regarding on the testbench where it shows fatal error while loading at the end of the modelsim simulation. Precisely, the errors are about as follows: i)# ** Error: (vsim-3389) C:/Users/Rheeshaalaen/Desktop/sw_pe_affine/sw_gen_testbench.v(9...
My problem here is regarding on the testbench where it shows fatal error while loading at the end of the modelsim simulation. Precisely, the errors are about as follows: i)# ** Error: (vsim-3389) C:/Users/Rheeshaalaen/Desktop/sw_pe_affine/sw_gen_testbench.v(...
# ** Fatal: Error occurred in protected context.# Time: 0 ps Iteration: 0 Protected: /fusiontestdebugtb/u_DebugApp/\nios2_qsys|enet_pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL\/inst/<protected> File: nofile# FATAL ERROR while loading design# Error loading design# Error...
# Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./<design>_run_msim_gate_verilog.do PAUSED at line 12 To work around this problem, simulate your gate-level netlist generated in the Quartus® II software version 10.1 with the ModelSim-Altera software ...