没有REF_CLK输出，然后我们用有源晶振进FPGA的PLL生成了一个125M时钟接到IMX6的ENET_REF_CLK ，现在...
As see on shematic few iMX6 boards, RGMII PHY put to MAC 125MHz to ENET_REF_CLK/ENET_TX_CLKENET_TX_CLK pin. What it for? I can't see any describe of this in manuals and RGMII not require this signal. Labels: i.MX6DL i.MX6Dual i.MX6Quad 2 Kudos Reply All forum topics Pre...
As see on shematic few iMX6 boards, RGMII PHY put to MAC 125MHz to ENET_REF_CLK/ENET_TX_CLKENET_TX_CLK pin. What it for? I can't see any describe of this in manuals and RGMII not require this signal. Labels: i.MX6DL i.MX6Dual i.MX6Quad 2 Kudos Reply All forum topics Pre...
As see on shematic few iMX6 boards, RGMII PHY put to MAC 125MHz to ENET_REF_CLK/ENET_TX_CLKENET_TX_CLK pin. What it for? I can't see any describe of this in manuals and RGMII not require this signal. Labels: i.MX6DL i.MX6Dual i.MX6Quad 2 Kudos Reply All forum to...
ENET1_TX_CLK is configured as ENET1_REF_CLK1, and should be an output from the PHY at 25MHz (I think). ENET2_RX_EN is configured as ENET1_REF_CLK_25M and should be an output from the IMX to the PHY at 25MHz. I'm using u-boot ATM, and have the following code: ...