I can only output the RMII_REF_CLK via pad GPIO1_IO00 as ALT1_CCM_ENET_PHY_REF_CLK_ROOT. Is there any way to get SAI1_MCLK to output a 50MHz RMII clock, or is there an error in the Processor Datasheet?0 Kudos Reply All
And the RMII I/F of i.MX25 is used. When Drive Strength on the device side is made small, the amplitude of FEC_TX_CLK(REF_CLK) becomes the 4Vpp degree.When Drive Strength on the device side is made big, the amplitude of FEC_TX_CLK becomes the 5.2Vpp degree. We want ...
IBUFDS #(.DIFF_TERM("FALSE"), // Differential Termination .IBUF_LOW_PWR("TRUE") // Low power="TRUE", Highest performance="FALSE".IOSTANDARD("DEFAULT") // Specify the input I/O standard ) IBUFDS_inst (.O(O), // Buffer output .I(I), // Diff_p buffer in...
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- Table 52. RMII Signal Timing(P.65)(We understand that it is a timing specification of REF_CLK when it is input to FEC_TX_CLK pin.) Best Regards,Yuuki Solved! Go to Solution. Labels: i.MX6SL Tags: fec_ref_clk ref_clk 0 Kudos Reply 1...
I can only output the RMII_REF_CLK via pad GPIO1_IO00 as ALT1_CCM_ENET_PHY_REF_CLK_ROOT. Is there any way to get SAI1_MCLK to output a 50MHz RMII clock, or is there an error in the Processor Datasheet?0 Kudos Reply All