In the recent HBM2E IO design, clock is transmitted differentially to the external DRAM and duty cycle distortion (DCD) could add to the differential clock due to traversing multiple stages in DRAM. At higher data rates, the DCD from the differential clock imposes restrictions on the timing mar...
Shih-Nung Wei, Yi-Ming Wang, Jyun-Hua Peng, and Yuandi Surya, "A range extending delay-recycled clock skew-compensation AND/OR duty-cycle-correction circuit," in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT), Apr. 2012....
Based on a comprehensive analysis of the principle of the DutyCycle Distortion (DCD),adopt an analog feedback method to achieve 20% -80% large range duty cycle correction from 0.4 to 4 GHz,while the error is less than 0.42%. The circuit is designed in 65 nm CMOS technology,which ...
although variations in the duty cycle can also be caused by the oscillator. Clock distribution networks use various elements such as buffers and inverters, often cascaded. These networks can introduce duty cycle distortion due to circuit and interconnect modeling inaccuracies, process variations, and th...
period. The drawback of this circuit is that the delay line covers ˜T/2 delay even if only a small duty cycle distortion (e.g. ±3% of T) needs to be corrected. (Reference: K. Agarwal; R. Montoye; “A Duty-Cycle Correction Circuit for High-Frequency Clocks”,VLSI Circuits,2006...
The present invention is related to integrated circuit (IC) clock systems and more particularly to maintaining duty cycle timing balance in ICs. 2. Background Description Large high performance very large scale integration (VLSI) chips like microprocessors are synchronized to an internal clock. A typ...
A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch
The present invention is related to integrated circuit (IC) clock systems and more particularly to maintaining duty cycle timing balance in ICs. 2. Background Description Large high performance very large scale integration (VLSI) chips like microprocessors are synchronized to an internal clock. A typ...
3.The duty cycle correction circuit according to claim 2, wherein the noise signal generator comprises:a delay unit configured to delay the up-down signal by a predetermined unit time and generate a plurality of delayed signals;a divider configured to divide the cycle of the up-down signal by...
A clock generator has a duty cycle correction circuit that adjusts the duty cycle to 50%. A modulator is an inverter with extra source-limiting transistors in series to the power and ground supplies.