Duty Cycle Distortion (DCD) Specifications Table 39. Worst-Case DCD on Cyclone® V I/O PinsThe output DCD cycle only applies to the I/O buffer. It does not cover the system DCD. Symbol–C6–C7, –I7–C8, –A7Unit MinMaxMinMaxMinMax Output Duty Cycle 45 55 45 55 45 55 % OCT Cal...
A method and system for modeling and calibrating duty cycle distortion (DCD) of a Serializer and Deserializer (SerDes) device, including first generating a clock DCD signal. Once the clock DCD signal is generated, it is calibrating based upon results obtained from a filtering process of the ...
DCDDuty Cycle Distortion(ANSI) DCDDynamic Content Delivery DCDDeseret Chemical Depot(Tooele, Utah) DCDDirectCD DCDDirectorate of Combat Developments(now Concepts and Requirements Directorate) DCDDiversity Career Day(Virginia) DCDDisk-Caching Disk
Low WF Distortion M1406-aQ175L-0p5 470-540nm Quartz 0.5 185 / 0.5 175 FixedVariable Low GVD M1418-aQ150L-1 470-800nm Quartz 1 185 / 0.5 175 FixedVariable Low GVD M1205-P80L-1,2,3 VIS PbMo04 1/2/3 90 / 0.5 80 FixedVariable M1206-P110L-1 VIS PbMo04 1 27 / 0.15 110...
DISTILL distillate 蒸馏,馏份DISTOR distortion 变形,畸变,失真DISTR distribution 分布,分配 DIV division 区分,除(法),部门 DIVR diverter 分流器,分流电阻,换向器DK desk 试验台,面板 DL dial 标度盘,千分表DLCONVY drag link conveyor 牵引杆输送机 DLD/COAL 蒸馏的煤焦油燃料TAR-F DL Y daily 每日的,日用...
1、电气与控制技术 load test and short-circuit test 负载试验(短路试验) plugging 反接制动与反向 intermittent periodic duty 反复短时工作制 feedback control 反馈控制 feedback loop 反馈回路 luminous intensity 发光强度 distributed capacitance 分布电容 split phase motor 分相电动机 fractional horsepower motor...
Duty cycle distortion (DCD) jitter modeling, calib 专利名称：Duty cycle distortion (DCD) jitter modeling,calibration and generation methods 发明人：Xingdong Dai,Weiwei Mao,Max J.Olsen,Geoffrey Zhang 申请号：US11968942 申请日：20080103 公开号：US08125259B2 公开日：20120228 专利内容由知识产权出版社提供...
A method and system for modeling and calibrating duty cycle distortion (DCD) of a Serializer and Deserializer (SerDes) device, including first generating a clock DCD signal. Once the clock DCD signal is generated, it is calibrating based upon results obtained from a filtering process of the ...
A method and system for modeling and calibrating duty cycle distortion (DCD) of a Serializer and Deserializer (SerDes) device, including first generating a clock DCD signal. Once the clock DCD signal is generated, it is calibrating based upon results obtained from a filtering process of the ...
A method and system for modeling and calibrating duty cycle distortion (DCD) of a Serializer and Deserializer (SerDes) device, including first generating a clock DCD signal. Once the clock DCD signal is generated, it is calibrating based upon results obtained from a filtering process of the ...