A duty cycle detector includes a first ring oscillator suitable for including an odd number of first inverters and generating a first periodic signal by using the first inverters, at least one inverter among the first inverters being enabled during a time interval when a clock has a first value...
the period when the square wave signal is high and subtract from the accumulated number, the number of clock pulses produced when the signal is low. A detector, in response to the final number held by the counter, determines whether the duty cycle is within the predetermined acceptable range....
Duty cycle detector 优质文献 相似文献 参考文献 引证文献Duty detector and duty cycle corrector including the same A duty detector includes a clock converter, a hold pulse generator, a first logic operator, and an up/down counter. The clock converter receives a clock signal to generate an up clo...
分类号 G01R29/02 申请人信息 申请(专利权)人 SK hynix Inc. 发明人IM Da In;SEO Young Suk 地址Icheon-siGyeonggi-doKR邮编- 代理人信息 代理机构 -代理人 - 摘要 A duty cycle detector may include a rising clock detection unit enabled in response to a first control signal; a falling clock dete...
A duty cycle detector including a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a clock signal having a first duty cycle and to provide a first oscillating signal having a first period proportional to the first duty cycle. The second circuit...
New methods to assess and improve LIGO detector duty cycle A network of three or more gravitational wave detectors simultaneously taking data is required to generate a well-localized sky map for gravitational wave sources, such as GW170817. Local seismic disturbances often cause the LIGO and Virgo ...
Although both of those phase detector circuits perform their intended function in a satisfactory manner, they possess certain characteristics which limit their utility. For example, the phase detector illustrated in Pat. No. 4,520,319 requires that the input frequency signal has a 50% duty cycle....
A duty cycle detector comprising a first circuit configured to receive clock cycles including a first level and a second level. The first circuit is configured to obtain a first value based on the length of the first level and to obtain second and third values based on the length of the se...
A duty cycle detector includes a first ring oscillator suitable for including an odd number of first inverters and generating a first periodic signal by using the first inverters, a
A signal detector whose output voltage approximates the true average to peak value of an applied signal of a generally arbitrary waveform employs current sources to regulate the charge-discharge duty cycle of an integrating storage device. The integrating storage device, such as an integrating capacit...