Dual-gate-material-based device design for unipolar metal oxide semiconductor-like carbon nanotube field effect transistors一种基于双栅材料的单极性类金属氧... 由于导电沟道-源/漏电极界面处可能发生的载流子带间隧穿,传统类金属氧化物半导体(MOS)碳纳米管场效应管呈现双极性传输特性,极大影响了器件性能的提高及...
The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical ...
A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region...
STRAPPED DUAL-GATE VDMOS DEVICE Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a s... SJ Alberhasky,DE Hart,...
The continued downward scaling of silicon MOSFET device dimensions below one tenth micron has presented new and serious challenges for future integrated circuit applications. Accordingly, new MOSFET structures, such as the dual-gate (FinFET) and the tri-Gate transistor, have been proposed to replace...
In this paper, we developed dual-gate enhancement/enhancement-mode (E/E-mode) and enhancement/depletion-mode (E/D-mode) AlGaAs/InGaAs pHEMTs for high-voltage and high-power device applications. These dual-gate devices had a higher breakdown voltage (Vbr) and maximum oscillation frequency (fmax...
This paper explores the performance of asymmetrical dual-k underlap spacer (ADKUS) SOI FinFET (device-D1) over the wide temperature range (200 K-450 K). An... N Jain,B Raj - NISCAIR-CSIR, India 被引量: 0发表: 2019年 Thermal stability analysis and performance exploration of asymmetrical...
A semiconductor device in which mutual diffusion of doped impurities occurring through an upper silicide electrode layer is prevented. A silicide electrode layer is doped with both the same degree of p-type impurities as the concentration of p-type impurities of the lower gate electrode layer and ...
A method of fabricating a semiconductor device may include forming active and field regions in a substrate; forming a gate trench in which the active and field regions are exposed; forming a gate insulating layer on a surface of the expo... Tai-Su PARK,Gun-Joong LEE,Young-Dong LEE,... ...
Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposi... H Zhu,J Beintner,BB Doris,... - US 被引量: 99发表: 2005年 Dual-gate GaAs FET: a versatile circuit component for MMICs A modeling procedure to obtain ...