Dual-gate-material-based device design for unipolar metal oxide semiconductor-like carbon nanotube field effect transistors一种基于双栅材料的单极性类金属氧... 由于导电沟道-源/漏电极界面处可能发生的载流子带间隧穿,传统类金属氧化物半导体(MOS)碳纳米管场效应管呈现双极性传输特性,极大影响了器件性能的提高及...
The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are ...
A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region...
STRAPPED DUAL-GATE VDMOS DEVICE Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a s... SJ Alberhasky,DE Hart,...
Dual gate logic device United States Patent 6891226 Abstract: The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. A single-crystal silicon wafer is utilized as the ...
The continued downward scaling of silicon MOSFET device dimensions below one tenth micron has presented new and serious challenges for future integrated circuit applications. Accordingly, new MOSFET structures, such as the dual-gate (FinFET) and the tri-Gate transistor, have been proposed to replace...
In this paper, we developed dual-gate enhancement/enhancement-mode (E/E-mode) and enhancement/depletion-mode (E/D-mode) AlGaAs/InGaAs pHEMTs for high-voltage and high-power device applications. These dual-gate devices had a higher breakdown voltage (Vbr) and maximum oscillation frequency (fmax...
A non-volatile memory device including a control gate pattern having a tunnel insulation pattern, a trap-insulation pattern, a blocking insulation pattern and a control gate electrode, which are stacked on a semiconductor substrate. A selection gate pattern is disposed on the semiconductor substrate ...
发明人: HANSON; JOHN W.,MACDOUGALL; JOHN D. 被引量: 54 摘要: A dual gate FET is described wherein the second channel is made more conductive than the first such that when employed as an amplifier or a mixer circuit, zero bias is required from the gates to ground.收藏...
Device fabrication and molecular connection Gate electrode arrays (8 nm Cr/60 nm Au) were patterned by photolithography and thermal evaporation on the silicon wafer with a 300 nm silicon oxide layer. Then, Al was deposited on top of Au/Cr electrodes to be connected. After that, the ...