The code that you give below is an assignment, but not registered. In this case, the Verilog and VHDL are equal. -James --- Quote Start --- --- Quote Start --- The real issue here is that signals can be used throughout a design and are usually registered, while ...
Currently I'm seeking for understanding why ModelSim 6.6d is capturing my data partly at the following (as expected) and the same edge of the clock: I'm trying to simulate the behaviour of a source synchronous interface (in VHDL) and generated some data in a testbench which I fee...
Currently I'm seeking for understanding why ModelSim 6.6d is capturing my data partly at the following (as expected) and the same edge of the clock: I'm trying to simulate the behaviour of a source synchronous interface (in VHDL) and generated some data in a testbench which I fee...
Currently I'm seeking for understanding why ModelSim 6.6d is capturing my data partly at the following (as expected) and the same edge of the clock: I'm trying to simulate the behaviour of a source synchronous interface (in VHDL) and generated some data in a testbench which I...
Currently I'm seeking for understanding why ModelSim 6.6d is capturing my data partly at the following (as expected) and the same edge of the clock: I'm trying to simulate the behaviour of a source synchronous interface (in VHDL) and generated some data in a testbench which I fe...