Currently I'm seeking for understanding why ModelSim 6.6d is capturing my data partly at the following (as expected) and the same edge of the clock: I'm trying to simulate the behaviour of a source synchronous interface (in VHDL) and generated some data in a testbench which I...
Currently I'm seeking for understanding why ModelSim 6.6d is capturing my data partly at the following (as expected) and the same edge of the clock: I'm trying to simulate the behaviour of a source synchronous interface (in VHDL) and generated some data in a testbench which I fe...
Currently I'm seeking for understanding why ModelSim 6.6d is capturing my data partly at the following (as expected) and the same edge of the clock: I'm trying to simulate the behaviour of a source synchronous interface (in VHDL) and generated some data in a testbench which I fe...