Ramana Reddy, "A Novel 1-Bit Full Adder Design Using DCVSL XOR/XNOR Gate and Pass Transistor Multiplexers", International Journal of Innovative and Exploring Engineering (IJITEE), ISSN:2278-3075, vol. 2, Issue-4, March 2013.Divakara P;Ramana R R.A novel 1-bit full adder design using ...
A novel multiplexer-based low-power full adder IEEE Trans. Circuits Syst. (2004) Si Shanthala et al. VLSI design and implementation of low power MAC unit with block enabling technique Eur. J. Sci. Res. (2009) A. Drozd, S. Antoshchuk, A. Rucinski, A. Martinuk, Parity prediction metho...
A new design for single bit full adder has been implemented using proposed XOR/XNOR gates and transmission gate multiplexer. Full adder designed with 14 transistors shows power dissipation of 655.6149W and maximum output delay 0.11055ns. Proposed adder circuit shows adequate noise margin of 3.2 V ...
Design and Power Dissipation Consideration of PFAL CMOS V/S Conventional CMOS Based 2:1 Multiplexer and Full Adder With the integration of circuits, number of gates and transistors are increasing per chip area. However with integration in every digital circuit, the ener... M Sharma,D Pandey,P...
Sheykhian, Design and simulation of a 2 × 1 all-optical multiplexer based on photonic crystals. Opt. Laser Technol. 151, 108021 (2022) Article MATH Google Scholar M. Abdollahi, F. Parandin, A novel structure for realization of an all-optical, one-bit half-adder based on 2D photonic ...
Gupta, Design of high speed ternary full adder and three-input XOR circuits using CNTFETs. In 2015 28th International Conference on VLSI Design (2015), pp. 292–297. http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=7031749. S.L. Murotiya, A. Gupta, Hardware-efficient low-...
Secondly, the position of the output cell is determined according to the Coulomb force between the electrons of the cell, so as to construct a low-power 5-input majority gate. Finally, a D flip-flop is designed using the proposed majority gate. The designed flip-flop has advantages, such ...
By using the full-custom design approach, the highest speed can be obtained by deliberate design at every stage of the design sequence. Minimizing the chip size by compacting as much as possible, we can obtain more chips from a wafer and consequently, the cost of a chip is minimized. At ...
Reliable circuit analysis and design using nanoscale devices We have presented a NANOLAB based fault model of 8-bit full adder, basic building block being 2:1 multiplexer. At each level, a Triple Modular ... R Kumawat,V Sahula,MS Gaur - International Conference on Communication & Electronics ...
The regular carry select adder (CSLA) is designed using RCA-RCA configuration. It uses two individual RCA with different anticipated carry input values (Cin = 0 and Cin = 1). After the calculation, the appropriate sum and carry-out will be selected using a multiplexer depending on the logic...