For delay optimization, this is becoming increasingly problematic since the existing models that possess such properties have become highly inaccurate in deep submicron technologies. Therefore, the first part of this thesis involves development of accurate and convex models for gate delay. The efficacy ...
So far, we have been able to investigate the various delay models in the MOS circuit. While these methods are simple and reasonably accurate, they should not serve as a complete replacement for CAD tools in situations where accuracy is crucial. However, these methods are suitable to provide a...
Effects of delay models on maximum power estimation of VLSI circuitsHsiao, M SRudnick, E MPatel, J HLu Junming, Lin Zhenghui, Effects of delay models on maximum power estimation of VLSI circuits, International Conference on ASIC, pp. 179 - 182, 2001...
In VLSI chip design flow, Static Timing Analysis (STA) is used for fast and accurate analysis of data-path delay. This process is fast because delay is picked from Look Up Tables (LUT) rather than conventional SPICE simulations. But accuracy of this method depends upon the underlying delay ...
State-of-the-art technologies for VLSI circuits give rise to various defect mechanisms that may cause a circuit to fail when operated at its designated speed of operation. Such defects are conventionally modeled by delay faults. In this paper, we review delay fault models used for circuits descr...
Transmission gates are used extensively in CMOS VLSI circuits. However, very few delay models have been developed for transmission gates or transmission-gate-based circuits. Accurate delay models are presented in this paper and compared with delays obtained from SPICE simulations. These delay models ...
In this paper, we examine delay models used in very large scale integration (VLSI) circuit testing. Our study is based on electrical-level simulation experiments. We present a comprehensive analysis of phenomena which significantly affect the actual delays but are not taken into account by the exi...
In the wide-sense stationary uncorrelated scattering (WSSUS) channel models [1], the delays of received waves arriving at a receive antenna are treated as uncorrelated. Therefore, for the WSSUS model, the underlying complex process is assumed as zero-mean Gaussian random proces and hence the RMS...
The study of asynchronous circuit behaviors in the presence of component and wire delays has received a great deal of attention. In this paper, we consider
electronic design automation processes for providing an estimate of a signal delay through an integrated circuit cell, the estimate of the signal delay being used in designing an integrated circuit device including said cell wherein the look-up table models signal delay using a non-linear function....