For DDR validation you may need to modify some python scripts to make it work (to match your DQ swizzle). The DQ mappings are as described... Each Nibble has 38h different orderings that can be used to move the bit order on any Nibble to accommodate bits 0-3 or 4-7 in different ...
(Identifier: PHY_SWIZZLE_MAP) Use Debug Toolkit If enabled, the AXI-L port will be connected to SLD nodes, allowing for a system-console avalon manager interface to interact with this AXI-L subordinate interface. Default value is false (Identifier: DEBUG_TOOLS_EN) Instanc...