A method is presented for employing contact over active gate to reduce parasitic capacitance. The method includes forming high-k metal gates (HKMGs) between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion, forming a first dielectric ...
Contact over active gate (COAG) structures with trench contact layers, and methods of fabricating contact over active gate (COAG) structures using trench contact layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is...
21. An electronic device comprising: a substrate having an active region with at least one gate stack formed thereon, the at least one gate stack having a first side and a second side and comprising a recessed gate; a spacer material on the substrate adjacent the first side and second side...
For high density, a novel self-aligned contact over active gate process and elimination of the dummy gate at cell boundaries are introduced. The transistors feature rectangular fins with 7nm fin width and 46nm fin height, 5th generation high-k metal gate, and 7th-generation strained silicon. ...
A method is presented for employing contact over active gate to reduce parasitic capacitance. The method includes forming high-k metal gates (HKMGs) between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion, forming a first dielectric ...
Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing selective deposition of masks in a three-color process.Wenhui Wang...
Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.Wenhui Wang...
A method is presented for employing contact over active gate to reduce parasitic capacitance. The method includes forming high-k metal gates (HKMGs) between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion, forming a first dielectric ...
Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing selective deposition of overlapping masks in a three-color process.Wenhui Wang...
First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating ...