These statements can be mapped to VITAL generics through well-defined transformations with elements separated by underscores. The actual selection of the timing values that are used is determined within the VHDL/VITAL model. In SDF, a conditional path delay consists of a condition applied to a ...
InSection 3.1.1, we introduced conditional variable assignments, which are a shorthand notation for variable assignments within if statements. VHDL similarly provides conditional signal assignments as a shorthand for signal assignment statements within if statements. The syntax rule is similar: conditional_...