Because of the merged data storage and computing units, compute-inmemory is becoming one of the desirable choices for data-centric applications to mitigate the memory wall bottleneck in von-Neumann architecture. In this chapter, the recent architectural designs and underlying circuit/device technologies for compute-in-memory are surveyed. The related design challeng...
中国科学院微电子研究所的李泠、岳金山团队在《IG-CRM: Area/Energy-Efficient IGZO-Based Circuits and Architecture Design for Reconfigurable CIM/CAM Applications》提出IG-CRM架构,一种基于IGZO(Indium-Gallium-ZineOxide,氧化铟镓锌)晶体管的可重构CIM(存内计算)和CAM(内容可寻址存储器)架构。该架构旨在解决现有C...
as well as the peripheral circuit designs with a focus on the analog-to-digital converters (section “Hardware Implementations for CIM Architecture”); a summary and outlook of the compute-in-memory architecture (Conclusionsection).
Non-volatile computing-in-memory (nvCIM) architecture can reduce the latency and energy consumption of artificial intelligence computation by minimizing the movement of data between the processor and memory. However, artificial intelligence edge devices with high inference accuracy require large-capacity nv...
Long, Y. et al. A ferroelectric FET-based processing-in-memory architecture for DNN acceleration.IEEE J. Explor. Solid State Comput. Devices Circuits5, 113–122 (2019). Google Scholar Chen, P. et al. Open-loop analog programmable electrochemical memory array.Nat. Commun.14, 6184 (2023). ...
In computer programming, macros are essentially rules, patterns or instructions that outline how input data should be mapped onto a given output. Their macro specifically applies to an on-chip non-volatile compute-in-memory (nvCIM) system, an architecture that combines a processor and a memory ...
The traditional Von Neumann architecture creates bottlenecks due to data movement. The compute-in-memory (CIM) architecture performs computations within memory bit-cell arrays, enhancing computational performance. Edge devices utilizing artificial intell
Certain aspects of the present disclosure provide a method, including: storing a depthwise convolution kernel in a first one or more columns of a CIM array; storing a fused convolution kernel in a second one or more columns of the CIM array; storing pre-activations in one or more input data...
Reconfigurable RRAM-CIM architecture A NeuRRAM chip consists of 48 CIM cores that can perform computation in parallel. A core can be selectively turned off through power gating when not actively used, whereas the model weights are retained by the non-volatile RRAM devices. Central to each core ...
Figure 5classifies hardware implementations of SRAM-CIM into three architectures.Figure 5a shows the introduction of the additional computational hardware without any other alteration to the memory architecture. In this architecture, the SRAM read operation provides data to the computational unit for NN ...