This chapter describes two embodiments of a novel and reconfigurable memory-based computing architecture which is designed to handle data-intensive kernels in a scalable and energy-efficient manner, suitable for next-generation systems.doi:10.1007/978-3-319-54840-1_4Robert Karam...
中国科学院微电子研究所的李泠、岳金山团队在《IG-CRM: Area/Energy-Efficient IGZO-Based Circuits and Architecture Design for Reconfigurable CIM/CAM Applications》提出IG-CRM架构,一种基于IGZO(Indium-Gallium-ZineOxide,氧化铟镓锌)晶体管的可重构CIM(存内计算)和CAM(内容可寻址存储器)架构。该架构旨在解决现有C...
PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. ACM SIGARCH Comput. Archit. News 44, 27–39 (2016). Google Scholar Zidan, M. A., Strachan, J. P. & Lu, W. D. The future of electronics based on memristive systems. Nat. ...
Non-volatile computing-in-memory (nvCIM) architecture can reduce the latency and energy consumption of artificial intelligence computation by minimizing the movement of data between the processor and memory. However, artificial intelligence edge devices with high inference accuracy require large-capacity nv...
In computer programming, macros are essentially rules, patterns or instructions that outline how input data should be mapped onto a given output. Their macro specifically applies to an on-chip non-volatile compute-in-memory (nvCIM) system, an architecture that combines a processor and a memory ...
Certain aspects of the present disclosure provide a method, including: storing a depthwise convolution kernel in a first one or more columns of a CIM array; storing a fused convolution kernel in a second one or more columns of the CIM array; storing pre-activations in one or more input data...
Reconfigurable RRAM-CIM architecture A NeuRRAM chip consists of 48 CIM cores that can perform computation in parallel. A core can be selectively turned off through power gating when not actively used, whereas the model weights are retained by the non-volatile RRAM devices. Central to each core ...
Fig. 1:Classic flash-based IMC architecture. Digital inputs are converted to analog voltages on word lines. Unlike a memory, multiple word lines can be active at the same time. All the cells along the bit line provide the multiplication of input voltage times the flash-cell conductance, whic...
TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks The training of neural network (NN) is usually time-consuming and resource intensive. Memristor has shown its potential in computation of NN. Especially for the metal-oxide resistive random access memory (RRAM), its ...
in-memory bitcells, a conventional choice is either a static-random-access-memory (SRAM) architecture or a dynamic-random-access-memory (DRAM) architecture. Of these two choices, a DRAM compute-in-memory architecture is advantageous as it is significantly denser than the comparable SRAM ...