A novel high-speed and high-precision voltage comparator has been proposed. In the comparator design, the Switched Operational Amplifier technique is adopted in the pre-amplifier stage to reduce the power consumption. The proposed voltage comparator is designed for 1MHz 12-bit SAR ADC under TSMC ...
for use in SAR ADCs Low power comparator for use in SAR ADCsLow power comparator for use in SAR ADCsdoi:US8258991 B2US
Yintang, "An offset cancellation technique in a switched-capacitor comparator for sar adcs," Journal of Semiconductors, vol. 33, no. 1, p. 015011, 2012. [Online]. Available: http://stacks.iop.org/1674-4926/33/i=1/a=015011Tong Xingyuan, Zhu Zhangming, Yang Yintang, "An offset ...
Design of a 0.2V 2.08nW 10-bit 1kS/s High Energy Efficiency SAR ADC with Dummy Capacitor Splitting Technique for Biomedical Applications This paper presents an ultra-low-voltage 10-bit successive approximation-register analog-to-digital converter (SAR ADC) based on the binary search algorith......
This thesis presents a high gain, low noise and low power dynamic residue amplifier and a low power, low noise dynamic comparator designed in TSMC 28nm process for a two step Pipelined SAR-ADC. The cascoded integrator dynamic residue amplifier (CIDRA) achieves a gain of 30dB with THD of 47...
Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC, as well as the linearity, and the optimized window size for the overall energy efficiency will vary with the DAC switching energy.Keywords: Skipping-window technique; DAC ...
Design of a 16-bit 500-MS/s SAR-ADC for low-power application TejenderSingh,SumanLata Tripathi, inElectronic Devices, Circuits, and Systems for Biomedical Applications, 2021 4.2Comparator Acomparatoris anelectronic circuitthat compares two analog input signals, so based on a comparison, it generat...
Comparator Power Minimization Analysis for SAR ADC Using Multiple Comparators Comparator power consumption is a major bottleneck to the power efficiency of a high resolution successive approximation register (SAR) analog-to-digital c... M Ahmadi,W Namgoong - 《IEEE Transactions on Circuits & Systems...
Design considerations for low power time-mode SAR ADC Also, noise and offset models describing the impact of the noise and offset on the timing error of time-domain comparator are presented. The results are... F Hua,H Xue,SB Kobenge,... - 《International Journal of Circuit Theory & Appli...
A prototype IV rail-to-rail SAR ADC for biomedical application has been implemented in 0.18 μm TSMC CMOS technology. It consumes 2.86 μW at 250kS/s and the figure of merit is 85.7 fJ/conversion-step. It shows that this work efficiently reduces 52% to 80% power consumption of the ...