This paper presents a novel footless single clock-phase three-stage comparator with internally generated regenerative voltage signals for low kickback noise and high speed. The preamplifier and clocked latch topology of dynamic comparators are considered in this brief. The proposed design has been ...
Yintang, "An offset cancellation technique in a switched-capacitor comparator for sar adcs," Journal of Semiconductors, vol. 33, no. 1, p. 015011, 2012. [Online]. Available: http://stacks.iop.org/1674-4926/33/i=1/a=015011Tong Xingyuan, Zhu Zhangming, Yang Yintang, "An offset ...
for use in SAR ADCs Low power comparator for use in SAR ADCsLow power comparator for use in SAR ADCsdoi:US8258991 B2US
Finally, the novel outcomes of proposed comparator are the optimization in required parameters such as power, delay, offset voltage and kickback noise for biomedical applications as compared to double tail dynamic comparator. The proposed consideration for SAR ADC can become a backbone for low power...
210MS/s 12-bit pipelined SAR ADC that can be used for mobile applications consists of various components that can reduce the precision and the power consumption of the device. It has been identified that the main component that causes a high power consumption in the circuit design is the dyna...
This thesis presents a high gain, low noise and low power dynamic residue amplifier and a low power, low noise dynamic comparator designed in TSMC 28nm process for a two step Pipelined SAR-ADC. The cascoded integrator dynamic residue amplifier (CIDRA) achieves a gain of 30dB with THD of 47...
Design of a 16-bit 500-MS/s SAR-ADC for low-power application 4.2 Comparator A comparator is an electronic circuit that compares two analog input signals, so based on a comparison, it generates an output [49]. In our proposed system, it compares the sampled signal and a VDAC output sign...
For an N-bit SAR ADC, if the probability of each digital output code is equal, the average switching energy of conventional, MS, CAS, Vcm-based, MAS methods can be derived as(1)Eavg,Conv=∑i=1N2N+1-2i2i-1CVref2(2)Eavg,MS=∑i=1N-12N-2-iCVref2(3)Eavg,CAS=∑i=1N-12N-2-...
Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC, as well as the linearity, and the optimized window size for the overall energy efficiency will vary with the DAC switching energy.Keywords: Skipping-window technique; DAC ...
Yang Siyu,Zhang Hui,Fu Wenhui,Yi Ting, and Hong Zhiliang State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China,.A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator.[J];Journal of Semiconductors,2011-03...