Built-in scan chains in the VLSI are utilized for experimental tests and proven to be very useful for SET evaluation. The specially designed test chip is developed and tested to find the relation between errors'
Allan L. Fisher and H.T. Kung,Synchronizing Large VLSI Processor Arrays, IEEE Transactions on Computers, Vol. C-34, No. 8, Aug. 1985, pp. 734–740. Google Scholar Donald F. Wann and Mark A. Franklin,Asynchronous and Clocked Control Structures for VLSI Based Interconnection Networks, IEEE ...
Leakage sources and possible solutions in nanometer CMOS technologies IEEE Circuits and Systems Magazine (2005) V. Adler et al. Repeater insertion to reduce delay and power in RC tree structures IEEE Asilomar Conference on Signals Systems and Computers (1997) J. Cong et al. Simultaneous buffer an...
A test chip prototype is designed and fabricated in 65 nm CMOS process (the chip die photo shown in Fig. 1b). The test chip includes three driver- less clock distribution structures as a form of metal mesh, clamper circuits for protection, D-flipflop-based active loads, an H-tree-based...
Generally, Wallace tree multipliers excel in speed but are larger in area; Booth multipliers are efficient for low-power applications, and Dadda multipliers strike a balance for general-purpose use. However, the existing literature does not specifically address the design and evaluation of approximate...
theprocessvariationbecomesanimportantfactorinthedesignofclockdistributionnetworksindeepsub-microntechnology,theportionoftheclockskewintroducedbytheprocessvariationsonthewirewidthandtheclockbuffersizecannolongerbeignored.Hybridstructures,whichconsistsofbothtreeandmeshstructures,aremoretolerantManuscriptreceivedOctober26,...
the second delay value for the second node, and the common delay value for the shared portion of the paths from the clock source through the clock tree to the first and second nodes; and outputting data indicative of the clock skew, wherein the determining and the outputting are performed ...
al, "A CMOS 500 Mbps/pin synchronous point to point link interface", IEEE, 1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 43-44, June, 1994. FIGS. 4 and 5 show examples of structures of the PDVC and the VCD (that have no relation with the Reference 2), ...
It is evident that there is a continuing need for improved clock bus structures for VLSI circuits. As the size of these circuits continues to increase, the distance between the terminal on the integrated circuit at which the train of clock pulses is received, and each of the circuit elements...
In prior art the most significant bit and some subset of the input register bit outputs are fed back to bit zero (the least significant or first bit) through an XOR (exclusive OR gate) tree. The larger the number of such feedbacks, the more gate delay time it takes to push them throug...