Power is one of the complex growing issues of VLSI system. Clocks are known to be major source of power consumption in digital circuits. In Clock tree synthesis to create the clustering algorithm for a design to achieve the low power and build the better clock tree in terms of clock skew ...
If the clock network of such a design is to be constructed using clock meshes to achieve lower clock skew, multiple meshes may be inserted as shown in Fig.1. This is a natural choice in terms of power consumption because each mesh can be gated whenever the block it spans is not actively...
It describes a post synthesis sleep transistor insertion (PSSTI), a heuristic clustering algorithm for sleep transistor insertion with the objective of total power minimization in a given clock tree. Sleep transistor sharing and sizing are deployed in order to meet the clock skew and wakeup delay ...
In this paper, one Non-Monte-Carlo (NMC) method is deployed to generate skew and skew variance by one-time analysis when a set of stochastic temperature maps is already provided. Moreover, one principal temperature–map analysis is developed to reduce the design complexity by clustering correlate...
Our method simultaneously performs (1) activity-aware register clustering that reduces clock tree power not only by clumping registers into a smaller area, but pulling the registers with similar activity pattern close to shut off more time for the resultant subtrees; (2) timing and activity based...
Mehta et al., Clustering and Load Balancing for Buffered Clock Tree Synthesis, Proceedings of the 1997 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Oct. 12, 1997, pp. 217-223. Primary Examiner: THOMPSON, ANNETTE M Attorney...
A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. A developed tool can be embedded in the existing clo
In particular, we introduce a new, multilevel partitioning heuristic that increases the efficiency of the clustering phase, one of the key steps of our methodology. The results demonstrate the effectiveness of our solution; in fact, power-delay product and timing overhead of the circuits ...
In order to achieve a shorter clock period by a clock tree with less wire length and less power consumption, a clustering based clock scheduling algorithm was proposed. In the algorithm, first registers are partitioned into clusters by their locations, and then clusters are modified to improve ...
ClusteringIn the framework of semi-synchronous circuit, in which clock is not necessarily distributed to all registers simultaneously, we introduce a fast clock-scheduling algorithm that takes a construction of clock-tree into account. Our algorithm tries to achieve a shorter clock period by repeating...