Power is one of the complex growing issues of VLSI system. Clocks are known to be major source of power consumption in digital circuits. In Clock tree synthesis to create the clustering algorithm for a design to
It describes a post synthesis sleep transistor insertion (PSSTI), a heuristic clustering algorithm for sleep transistor insertion with the objective of total power minimization in a given clock tree. Sleep transistor sharing and sizing are deployed in order to meet the clock skew and wakeup delay ...
Mehta et al., Clustering and Load Balancing for Buffered Clock Tree Synthesis, Proceedings of the 1997 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Oct. 12, 1997, pp. 217-223. Primary Examiner: THOMPSON, ANNETTE M Attorney...
A system for performing slew-driven clock tree synthesis includes pair selection and cost metric definition considering physical distance for efficient sink clustering; slew and ske
Our method simultaneously performs (1) activity-aware register clustering that reduces clock tree power not only by clumping registers into a smaller area, but pulling the registers with similar activity pattern close to shut off more time for the resultant subtrees; (2) timing and activity based...
In particular, we introduce a new, multilevel partitioning heuristic that increases the efficiency of the clustering phase, one of the key steps of our methodology. The results demonstrate the effectiveness of our solution; in fact, power-delay product and timing overhead of the circuits ...
In order to achieve a shorter clock period by a clock tree with less wire length and less power consumption, a clustering based clock scheduling algorithm was proposed. In the algorithm, first registers are partitioned into clusters by their locations, and then clusters are modified to improve ...
Very-large-scale integration (VLSI) circuitsComputer-Aided Design (CAD)clock-gatingpower reductionactivity correlationclusteringClock gating is an effective way to reduce the dynamic power in digital sequential circuits. In this paper, a gate-level activity correlation-based clustering clock-gating (CCG...
ClusteringIn the framework of semi-synchronous circuit, in which clock is not necessarily distributed to all registers simultaneously, we introduce a fast clock-scheduling algorithm that takes a construction of clock-tree into account. Our algorithm tries to achieve a shorter clock period by repeating...
In this paper, a clock control strategy is implemented in VLSI circuit for power reduction. The analysis of clustering system and the circuit slack values are taken. The ideal cluster of the circuit is defined by the proposed approach in an efficient manner and the path is defined based on ...