核对端口/clk_wiz_0/clk_和其他相关端口的freq_hz属性是否一致: 在Block Design视图中,检查连接到clk_wiz_0/clk_out1的所有端口和模块。 确认这些端口和模块的时钟输入频率是否与clk_wiz_0/clk_out1的输出频率相匹配。 如果不一致,修改/clk_wiz_0/clk_或其他相关端口的freq_hz属性值以确保它们匹配: 如果...
CRITICAL WARNING: [IP_Flow 19-973] Failed to create IP instance 'design_1_clk_wiz_0_0'. Error during customization. ERROR: [ #UNDEF] Error occurred while initializing 'clk_wiz_0' Tcl error in update procedure while setting value 'MMCM' on the parameter 'PRIMITIVE'....
> In clk-xlnx-clock-wizard.c, the function clk_wzrd_probe will check if > there is "xlnx,nr-outputs" property, if not, the probe will return > error. Add "xlnx,nr-outputs" property for clk_wiz_0 node to avoid probe > failure. > > Signed-off-by: Quanyang Wang <quanyang.w....