Make sure to follow step 1 and step 2, note the PLL_N change from 60 to 3 as CLKout5_DIV = divide by 20. Could you attach an image of the waveform you are seeing? 2:Frequency calibration flow chart, blue mark, valid oscin this effective how to know? This pin foot is directly ...
The default divider ratio is divide-by-one. Table XIII. DMCLK (Internal) Rate Divider Settings MCD2 0 0 0 0 1 1 1 1 MCD1 0 0 1 1 0 0 1 1 MCD0 0 1 0 1 0 1 0 1 DMCLK Rate MCLK MCLK/2 MCLK/3 MCLK/4 MCLK/5 MCLK MCLK MCLK Serial Clock Rate Divider The AD73360L ...
The default divider ratio is divide-by-one. Table XV. DMCLK (Internal) Rate Divider Settings MCD2 0 0 0 0 1 1 1 1 MCD1 0 0 1 1 0 0 1 1 MCD0 0 1 0 1 0 1 0 1 DMCLK Rate MCLK MCLK/2 MCLK/3 MCLK/4 MCLK/5 MCLK MCLK MCLK Serial Clock Rate Divider The AD73360 features...