I => clk3 -- Clock buffer input);我用这个map的时候却总是报错DCM_SP symbol "DCM_SP_inst1" (output signal=clk3) has anequation that uses input pin I0,which no longer has a connected signal.Please ensure that all the pins used in the equation for this LUT have...
Verilog 中关于例化的问题以下是主程序中的一个例化模块: system_ctrl #( .DUTY_CYCLE (DUTY_CYCLE), .DIVIDE_DATA (DIVIDE_DATA), .MULTIPLY_DATA (MULTIPLY_DATA) ) system_ctrl_inst ( .clk (clk), .rst_n (rst_n), .clk_c0 (clk_vga), .sys_rst_n (sys_rst_n) ); 这种例化是什么意思?