这一类clock具有固定的factor(即multiplier和divider),clock的频率是由parent clock的频率,乘以mul,除以div,多用于一些具有固定分频系数的clock。由于parent clock的频率可以改变,因而fix factor clock也可该改变频率,因此也会提供.recalc_rate/.set_rate/.round_rate等回调。以第一行的clk为例,这里的"sys_pll1_50m"...
1. UART6有两种时钟源选择APLL\UPLL(可通过技术手册查看),如图 clk[uart6_aplldiv] = nuc970_clk_divider("uart6_aplldiv", "apll", REG_CLK_DIV5, 16, 3); clk[uart6_uplldiv] = nuc970_clk_divider("uart6_uplldiv", "upll", REG_CLK_DIV5, 16, 3); 2. UART6有两种时钟源选择APLL\UPLL...
For example, the duty cycle of a divider may depends on the raw divider setting (ratio = N / div) , which is controlled by the CCF. In such case, going through the pwm framework to control the duty cycle ratio of this clock would be a burden. A clock provider is not required to ...
These can also be seen in the BOARD_BootClockRUN function I mentioned previously, but the clock divider you're changing should be the only needed function for this purpose. Please let me know if you need any more information. Best regards, Sebastian 0 Kudos Reply 04-10-2020 ...
- the .set_parent method theoretically could be supported on some clocks (the parent would have to be one of the TBG clocks) - the .set_rate method would have to try all the divider values to find the best approximation of a given rate, and it doesn't seem like this should be ...
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clk[cpu_div]=nuc970_clk_divider("cpu_div","sys_div",REG_CLK_DIV0,16,1); clk[cpu_gate]=nuc970_clk_gate("cpu_gate","cpu_div",REG_CLK_HCLKEN,0); // HCLK1 & PCLK clk[hclk1_div]=nuc970_clk_fixed_factor("hclk1_div","cpu_div",1,2); ...
Switching back SDCLK source to Device Clock and now setting DCLK source to Divider, I can also see that the output section 1 to 32 DCLK divider is also not operating properly. It tries to divide, but some pulses get merged and prolonged in a seemingly random manner. ...
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These can also be seen in the BOARD_BootClockRUN function I mentioned previously, but the clock divider you're changing should be the only needed function for this purpose. Please let me know if you need any more information. Best regards, Sebastian 0 Kudos Reply ...