#define CONFIG_SYS_CLK_FREQ 66666666 #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); #endif /* * DDR Setup */ 3 changes: 1 addition & 2 deletions 3 include/configs/alt.h Original file line numberDiff line numberDiff line change @@ -34,8 +34,7 @@ #define CONFIG_...
sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; sys_info->freq_ddrbus = get_board_sys_clk(); else #endif #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) @@ -526,7 +526,7 @@ void get_sys_info(sys_info_t *sys_info) plat_ratio = (gur->porpll...
=> hmc_DDR_status_local_cal_fail goes high, => hmc_DDR_status_local_cal_success goes low. => But If I set a MEM_CLK_FREQ = 400MHz, the calibration always seems OK (hundred tests). I'd like to know, how the increase of MEM_CLK_FREQ will affect the DDR cali...
With rawclk_freq moved to display runtime info, xe has no users left for them. Signed-off-by: Jani Nikula <jani.nik...@intel.com> --- drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 - drivers/gpu/drm/xe/xe_device_types.h | 6 --- 2 files changed, 7 deletions(-) ...
DDR clk: 533MHz L3 clk: 220MHz HDVPSS clk: 220MHz HDVICP clk: 450MHz ISS clk: 560MHz DSP clk: 750MHz Then found if swMsPrm.layoutPrm.outputFPS = 30; actual swMs framerate is larger than 30. (I means (total output frames)/(total processed time) ) ...
I am confused about the SYSCLK_FREQ rcw value on the T4160RDB and I referred the T4240RM.pdf for RCW filed discription. Here is the hard-coded RCW value for T4160RDB: Reset Configuration Word (RCW): Data.Set DBG:0x01000000 0x1406000F Data.Set DBG:0x01000001 0x0A080808 Data.Set...
pll6_freq = 720 对于没有配置的，系统设置频率为默认值 4.模块加载 编进内核，无需加载。5.依赖...
+ RUNTIME_INFO(dev_priv)->rawclk_freq = freq; + drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq); } static int i915_cdclk_info_show(struct seq_file *m, void *unused) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h ...
The project is built on top of Intel's PCIE Gen3 x8 DMA reference design for Arria 10 GX Development Kit. EMIF and PCIE modules are both Intel's reference IP for DDR interfacing and PCIE-based DMA operations, respectively. The user logic (MY CORE) is a quite complex ...
ERROR: could not get clock /soc/busfreq:axi_alt_sel(10) imx6_busfreq busfreq.13: busfreq_probe: failed to get axi_alt_sel_clk imx6_busfreq: probe of busfreq.13 failed with error -2 Bus freq driver module loaded futex hash table entries: 256 (order: 2, 16384 bytes) ...