Memory cell structure of SRAMMemory cell structure of SRAM一种静态随机存取记忆体的记忆胞的结构,SRAM元件,其包括位于基板的深N井区中的SRAM记忆胞. A static random access memory cell structure of the memory, SRAM components, which includes a deep N-well region of the substrate in the SRAM memory...
The structure of SRAM cell is provided to improve the low Vss characteristics with zero voltage difference ( Vss), and is composed so that the bit line (B/L) and the bit line bar of a cell (d) form a common Vss contact (g) in order to remove the voltage difference( Vss).KWON, ...
SRAM cell structure and manufacturing method thereofX-ray microdiffractionthin filmsstrain/stressA static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the ...
This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free fea... MH Tu,JY Lin,MC Tsai,... - Solid-State Circuits, IEEE Journal of 被引量: 100发表: 2012年 0.7V two-port 6T SRAM memory cell...
Problem to be solved: to solve the problem that the channel length of the word transistor is increased without increasing the cell area, and the stability of the cell operation can be raised, and the signal is transmitted through the diffusion layer, and the SRAM cell structure is solved . ...
PURPOSE: To provide a SRAM cell structure in which operational stability of cell is enhanced by increasing the channel length of a word transistor without increasing cell area and signal can be transmitted through a diffusion layer with no problem. ;CONSTITUTION: In a SRAM memory cell structure ...
A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set ...
United States Patent US9613682 Note: If you have problems viewing the PDF, please make sure you have the latest version ofAdobe Acrobat. Back to full text
This invention reports a two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. With an unique structure by connecting the source terminal of an NMOS device in the SRAM cell to the write word line, this...
One illustrative 6T SRAM cell structure disclosed herein includes a first active region with a first N-type pass gate transistor, a first N-type pull-down transistor and a first P-type pull-up transistor, each of which are formed in and above the first active region, wherein the first N...