I'm a java coder to begin with so sometimes verilog can be confusing at times and this is one of those times. What I'm trying to do is to call a module inside an if that is inside an always block. When I try to do that it gives me an error that says "task 'module_name...
@titan73 the verilog code doesn't make any sense. module test(a, b, z); input a; wire a; input b; wire b; output z; wire z; STD_CELL _00_ ( .A(flops[1]), .B(in_ports[1]), .Z(out_ports[1]) ); endmodule flops,in_ports,out_ports are uses but not initialized and ...