I'm a java coder to begin with so sometimes verilog can be confusing at times and this is one of those times. What I'm trying to do is to call a module inside an if that is inside an always block. When I try to
I need to call [b] Verilog tasks defined in a module <> hierarchy [/b], from my [b] classes in SystemVerilog [/b]. How can it be made possible ??even defining them as extern task<> in SystemVerilog, it's giving compile time error, saying no module defined.I...