Calibration techniques can be applied to measure and correct for such error in an SAR ADC using decide-and-set switching. Specifically, a calibration technique can expose the effective bit weight of each bit under test using a plurality of special input voltages and storing a calibration word ...
For the pipelined ADC proposed in [2], simulation results show that the proposed techniques can achieve a 60X reduction in the calibration time. 展开 关键词: digital calibration calibratoin acceleration least-mean-square (LMS) adapatation ADC testing mixed-signal testing 被引量: 34 ...
[1] I. Young, D. Hodges, and P. Gray, “Analog NMOS sampled-data recursive filter,” in 1977 IEEE Int. Solid-State Circuits Conf. Dig. Technical Papers, Feb. 1977, pp. 156–157. [2] J. L. McCreary and P. R. Gray, “All-MOS chargeredistributionanalog-to-digital conversion techn...
i ABSTRACT In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs. To reduce total test time, optimized cali...
Successive approximation register (SAR) analog-to-digital converter (ADC) is an attractive architecture for its outstanding energy efficiency [1,2], while its application in high-precision area is still under developed devoting on calibration techniques to solve nonidealities such as offset error, ga...
A New Self-Calibration Technique in Successive Approximation A/D Converters This paper deals with a novel algorithm to be applied in self-calibration techniques for successive approximation analog–to-digital converters. It is based on a logarithmic approach. Measurements, performed on a test-chip, ...
Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy. Presents the details of a fast and accurate correlation-based background digital calibration scheme in the context of a 1.5-bit-per-stage pipelined or cycl... J Li,UK Moon - 《IEEE Transactions on Circuits &...
Time interleaving is one of the most efficient techniques employed in the design of high-speed sampled-data systems. However, the mismatches appearing amon... Sai-Weng Sin,,Chio, U.-F,U Seng-Pan,... - 《IEEE Transactions on Circuits & Systems II Express Briefs》 被引量: 40发表: 2008年...
IEEETRANSACTIONSONCIRCUITSANDSYSTEMS—II:ANALOGANDDIGITALSIGNALPROCESSING,VOL.50,NO.9,SEPTEMBER2003531 BackgroundCalibrationTechniquesforMultistage PipelinedADCsWithDigitalRedundancy JipengLi,StudentMember,IEEE,andUn-KuMoon,SeniorMember,IEEE Abstract—Theproposeddigitalbackgroundcalibration scheme,applicabletomultistage(...
bitsofENOBat1,MHzinputwitha600一MS/ssamplingrate.ThedisadvantageoffoldingisthelargersusceptibilitytodevicemismatchespeciallywhenimplementedinCMOStechnologies,whichcanbemitigatedbydigitalcalibration.Digita1calibrationtechniqueshavebeenprovedtobeeficientforpipelineADCsl2—41.foldingandin—terpolationADCSDJinperformance...