“A 10-Gb/s burst-mode CDR IC in 0.13μm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf., vol. 1, Feb. 2005, pp. 228-229.M. Nogawa, K. Nishimura, S. Kimura, T. Yoshida, T. Kawamura, M. Togashi, K. Kumozaki, and Y. Ohtomo, "A 10 Gb/s Burst-Mode CDR IC in...
burst-modeCDRforGPONOLTapplications.Ourdesignis basedonacommerciallyavailableSONETCDRoperatedin2× oversamplingmode. I.INTRODUCTION Passiveopticalnetworks(PONs)areanemergingaccess networktechnologythatprovidesalow-costmethodof deployingfiber-to-the-home.Fig.1showsanexampleofa ...
Suzuki, K. Nakura, S. Kozaki, H. Tagami, M. Nogami and J. Nakagawa, "82.5 Gsample/s (10.3125 GHz 3 8 phase clocks) burst-mode CDR for 10G-EPON systems", EL, Vol. 45 No. 24, 2009, pp. 1261-1263N. Suzuki, K. Nakura, S. Kozaki, H. Tagami, M. Nogami, and J. Nakagawa....
转格式 178阅读文档大小:31.0K7页30349b0287上传于2017-09-26格式:DOC 6221244 mbs burst-mode cdr for gpons:6221244 mbs突发模式cdr for gpon 热度: [OFC 2013 Tutorial OW3G.4] Burst-mode Receiver Technology for… 热度: A Burst-Mode APD-ROSA Using Reset Signal With Less Than 100 ns Response for...
This paper compares two burst-mode clock and data recovery (BM-CDR) techniques suitable for bursty upstream data transmission, namely a gated voltage controlled oscillator (GVCO) and an oversampling clock phase alignment (CPA). Numeric models were deduced with timing jitter and duty cycle distortio...
A quick-lock reference-clock-less all-digital burst-mode CDR is proposed. Since the proposed CDR resumes from a standby state soon after a 4-bit preamble and consumes no dynamic power in its stand...
a multibitrate burst-mode CDR circuit with bit-rate discrimination function from 52 to 1244Mbs IEEE PHOTONICS TECHNOLOGY LETTERS,VOL.13,NO.11,NOVEMBER20011221 A Multibitrate Burst-Mode CDR Circuit With Bit-Rate Discrimination Function From52to1244Mb/s Shoukei Kobayashi,Member,IEEE,and Masashi ...
C. Liang "A 10 Gbps burst-mode CDR circuit in 0.18 $\mu{\hbox {m}}$ CMOS", Proc. IEEE Custom Integrated Circuits Conf. (CICC) , 2006C.-F. Liang; S.-C. H.; S.-l. Liu, "A 10Gbps Burst-Mode CDR Circuit in 0.18yym CMOS" Proc. CICC, pp. 5 9 9 - 6 0 2...
Burst Mode CDR in 65nm CMOSdoi:10.1109/isscc.2011.5746386Abiri, BehroozSheikholeslami, AliTamura, HirotakaKibune, Masaya
A quick-lock reference-clock-less all-digital burst-mode CDR is proposed. Since the proposed CDR resumes from a standby state soon after a 4-bit preamble and consumes no dynamic power in its standb...