“A 10-Gb/s burst-mode CDR IC in 0.13μm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf., vol. 1, Feb. 2005, pp. 228-229.M. Nogawa, K. Nishimura, S. Kimura, T. Yoshida, T. Kawamura, M. Togashi, K. Kumozaki, and Y. Ohtomo, "A 10 Gb/s Burst-Mode CDR IC in...
II.BURST-MODECDR ThemainbuildingblocksoftheBM-CDRareaSONET CDR,a1:16deserializer,abytesynchronizer,andaphase picker(seeFig.2).TheBM-CDRsupportsthreemodesof operation:1)conventionalmode,2)2×oversamplingmode, and3)burstmode.Theconventionalmodeofoperation effectivelymakestheBM-CDRlooklikeaconventional SONET...
Suzuki, K. Nakura, S. Kozaki, H. Tagami, M. Nogami and J. Nakagawa, "82.5 Gsample/s (10.3125 GHz 3 8 phase clocks) burst-mode CDR for 10G-EPON systems", EL, Vol. 45 No. 24, 2009, pp. 1261-1263N. Suzuki, K. Nakura, S. Kozaki, H. Tagami, M. Nogami, and J. Nakagawa....
6221244 mbs burst-mode cdr for gpons:6221244 mbs突发模式cdr for gpon 热度: [OFC 2013 Tutorial OW3G.4] Burst-mode Receiver Technology for… 热度: A Burst-Mode APD-ROSA Using Reset Signal With Less Than 100 ns Response for 1G 10G-EPON Dual-Rate Optical Transceivers ...
This paper compares two burst-mode clock and data recovery (BM-CDR) techniques suitable for bursty upstream data transmission, namely a gated voltage controlled oscillator (GVCO) and an oversampling clock phase alignment (CPA). Numeric models were deduced with timing jitter and duty cycle distortio...
82.5 Gsample/s (10.3125 GHz x 8 phase clocks) burst-mode CDR for 10G-EPON systems A high-speed 82.5 Gsample/s sampling IC and its incorporated burst-mode CDR compliant for 10G-EPON systems are presented. The 82.5 Gsample/s sampling CDR s... N Suzuki,K Nakura,S Kozaki,... - 《...
A Multibitrate Burst-Mode CDR Circuit With Bit-Rate Discrimination Function From52to1244Mb/s Shoukei Kobayashi,Member,IEEE,and Masashi Hashimoto Abstract—In this letter,we fabricate and assess a clock and data recovery(CDR)circuit with a bit-rate discrimination(BRD)func-tion that can receive ...
I am writting here to ask something about burst bit error rate test. I wonder whether you can tell me how can you solve the burst clock and data recovery, or you have a better solution than the burst mode CDR. Since we have a project that we need to deal with the GPON/EPON OLT up...
Burst Mode CDR in 65nm CMOSdoi:10.1109/isscc.2011.5746386Abiri, BehroozSheikholeslami, AliTamura, HirotakaKibune, Masaya
A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC 来自 mendeley.com 喜欢 0 阅读量: 27 作者:J Terada,K Nishimura,S Kimura,H Katsurai,N Yoshimoto,Y Ohtomo 被引量: 21 年份: 2008 收藏 引用 批量引用 报错 分享 全部来源 求助全文 mendeley.com 引证文献...