The tile or wafer may include semiconductor device(s) for burn-in testing. The apparatus may include a thermal control unit to regulate testing temperature and/or drive electronics for powering the socket. The apparatus may include an inlet for gas pressure from a pressure source. The apparatus...
Burn-in testing simulates extended periods of work environment by subjecting products to accelerated temperature and voltage changes over a short time. This testing method is crucial for assessing the reliability of electronic components and is divided into three sections of the Bathtub Curve: Infant...
Test and burn-in apparatus in-line system using apparatus, and test method using the system 一种用于测试半导体器件的装置,其允许在相同的阶段进行包括老化在内的多种测试. An apparatus for testing a semiconductor device, which allows for a variety of ... 孟柱石 被引量: 6发表: 1999年 ...
Burn-in testing attempts to weed out failures from stage 1 of the“bathtub” curve for reliability of electronics equipment, which gives the failure rate vs. time plot of electronic components. Advertisement Advertisement Partner Content Cadence: Leading the EDA Industry with AI-Powered Platforms ...
Burn-in testing apparatus and method An integrated circuit (IC) package testing apparatus (Figure 5) integrates a temperature sensor (48), heater (or cooler) (44), and controller (42) within a... BJ Denheyer,GB Kuenster,CA Lopez - WO 被引量: 12发表: 2005年 Test fixture for electronic...
Wafer burn-in testing circuit of semiconductor memory device A wafer burn-in test circuit for a semiconductor memory device includes: a word line driver which is connected to a word line, is controlled by a low decoding signal generated from the low decoder, inputs a boosting voltage through ...
PURPOSE: To simply conduct a burn-in test of an IC chip and to prevent burning of the chip during testing. ;CONSTITUTION: In order to conduct a burn-in test of an IC chip, temperature stress means is provided at a wafer holding base by using a probe unit, and electric stress means ...
Aehr Test Systems is the leader in wafer level burn-in for silicon carbide (SiC), gallium nitride (GaN), optical photonics, and memory integrated circuits.
A method for testing a multi-chip package formed of different types of semiconductor devices, using an integrated burn-in test program which can reduce throughput time, reduce the possibility of error by an operator, and reduce workload. A multi-chip package is tested in burn-in equipment capa...
Aehr Test Systems is the leader in wafer level burn-in for silicon carbide (SiC), gallium nitride (GaN), optical photonics, and memory integrated circuits.