宽的输入电压范围,加上在电池瞬态过程中保持恒定输出电压的能力,使MAX25431成为汽车应用的理想选择。 对于轻载应用,一个逻辑输入(FSYNC)允许设备在跳跃模式下操作以减少电流消耗,或固定频率,强制pwm模式。FSYNC消除了频率变化,并有助于减少电磁干扰。MAX25431控制器提供了从220kHz到2.2MHz的电阻可编程的开关频率,并可以...
宽的输入电压范围,以及在电池瞬态过程中保持恒定输出电压的能力,使该设备成为汽车应用的理想选择。在轻载应用中,逻辑输入(FSYNC)允许设备在跳跃模式下工作以减少电流消耗,或固定频率,强制pwm模式以消除频率变化,并帮助最小化EMI。保护功能包括循环电流限制和热关闭自动恢复。MAX20048是一个小的4mm x 4mm 24引脚TQFN...
高达2.1MHz的高开关频率允许使用小尺寸外部元件、降低输出纹波,且保证无AM波段干扰。开关频率固定为400kHz或2.1MHz。FSYNC输入的可编程能力支持三种模式,实现最优性能。强制固定频率、超低静态电流的跳脉冲模式 、锁相同步至外部时钟。扩频选项可最大程度降低EMI干扰。
fSYNC VSYNCH VSYNCL RT = 144kΩ RT = 72kΩ RT Open or to VCC5V RT = 0V RT = 72kΩ 220 245 265 kHz 420 450 485 kHz 90 120 145 kHz 470 575 650 kHz 580 mV 140 600 kHz 3.2 V 0.5 V CLKOUT Output High CLKOUT Output Low CLKOUT Frequency Dither Mode Setting Current Source ...
fSYNC HICCUP MODE fSW(SS) fSW(SYNC) VFB = 0 V VFB = 0.2 V VFB = 0.6 V VFB = 0.8 V 0 V < VFB < 0.2 V 0.2 V < VFB < 0.4 V 0.4 V < VFB – 0.12 × fOSC –– 0.43 × fOSC –– 0.93 × fOSC –– fOSC –– fSYNC/4 –– fSYNC/2 –– fSYNC –––––––– ...
yes checking for F_FULLFSYNC... no checking for O_CLOEXEC... yes checking for __builtin_prefetch... yes checking for _mm_prefetch... yes checking for strong getauxval support in the system headers... no checking for weak getauxval support in the compiler... yes checking for Berkeley...
external resistor 8.4 fSYNC Buck synchronization range 9.0 Internal Gate-Driver Supply External clock input 9.1 VREG Internal regulated supply Load regulation VIN = 8 to 18 V, VEXTSUP = 0 V, SYNC = high IVREG = 0 to 100 mA, VEXTSUP = 0 V, SYNC = high 9.2 9.3 9.4 9.5 9.6 10.0 VREG...
external resistor fSYNC Buck synchronization range INTERNAL GATE-DRIVER SUPPLY External clock input VREG Internal regulated supply Load regulation VIN = 8 V to 18 V, EXTSUP = 0 V, SYNC = high IVREG = 0 mA to 100 mA, EXTSUP = 0 V, SYNC = high VREG(EXTSUP) Internal regulated supply Lo...
VBAT SW DREG GREG SBCLK FSYNC SDIN SDOUT AD1 AD2 SDA SCL SDZ IRQZ Power Management Digital Audio Interface Control Interface Clocking Digital Core Filters / Control Efficiency Algos VBAT, PVDD, and Temp Monitor Device Protections Boost PVDD Class-D Amp OUT_P OUT_N IV Sense ADCs Monitor ADC...
UVLO, Standby, and Clock Synchronization (a) VSUPPLY MCU UVLO/SYNC www.ti.com FSYNC Figure 9-14. UVLO, Standby, and Clock Synchronization (b) If the UVLO function is not required, the shutdown and clock synchronization functions can be implemented together by using one push-pull output of...