CONFIG_ETHERNET=y CONFIG_NET_VENDOR_XILINX=y CONFIG_XILINX_PHY=y CONFIG_AXIENET_HAS_MCDMA=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_MACB_USE_HWSTAMP=y # CONFIG_CAVIUM_PTP is not set CONFIG_XILINX_AXI_EMAC_HWTSTAMP=y CONFIG_PPS=y # CONFIG_PPS_DEBUG is not...
75218 - 2020.1 Zynq UltraScale+ MPSoC: AXI Ethernet driver in specific MCDMA configuration throws swiotlb full error with jumbo frames Description In my ZCU102 design which includes 10G and MCDMA (32-bit), I am seeing a swiotlb buffer full error when the MTU is set to 9000. ...
int__maybe_unusedaxienet_mcdma_rx_probe(structplatform_device*pdev, structaxienet_local*lp, structnet_device*ndev); #endif #ifdefCONFIG_AXIENET_HAS_MCDMA voidaxienet_tx_hwtstamp(structaxienet_local*lp, Expand Down 925 changes: 24 additions & 901 deletions925drivers/net/ethernet/xilinx/xilinx_ax...
若想让ZYNQ的PS与PL两部分高速数据传输,需要利用PS的HP(高性能)接口通过AXI_DMA完成数据搬移,这正符合PG021 AXI DMA v7.1LogiCORE IP Product Guide中介绍的AXI DMA的应用场景:The AXI DMA provides high-speed data movement between system memory and an AXI4-Stream-based target IP such as AXIEthernet. ...
30 changes: 16 additions & 14 deletions 30 drivers/net/ethernet/xilinx/xilinx_axienet_mcdma.c Original file line numberDiff line numberDiff line change @@ -222,7 +222,7 @@ int __maybe_unused axienet_mcdma_tx_q_init(struct net_device *ndev,...
若想让ZYNQ的PS与PL两部分高速数据传输,需要利用PS的HP(高性能)接口通过AXI_DMA完成数据搬移,这正符合PG021 AXI DMA v7.1 LogiCORE IP Product Guide中介绍的AXI DMA的应用场景:The AXI DMA provides high-speed data movement between system memory and an AXI4-Stream-based target IP such as AXI Ethernet...
若想让ZYNQ的PS与PL两部分高速数据传输,需要利用PS的HP(高性能)接口通过AXI_DMA完成数据搬移,这正符合PG021 AXI DMA v7.1 LogiCORE IP Product Guide中介绍的AXI DMA的应用场景:The AXI DMA provides high-speed data movement between system memory and an AXI4-Stream-based target IP such as AXI Ethernet...
2 changes: 1 addition & 1 deletion2drivers/net/ethernet/xilinx/Makefile Original file line numberDiff line numberDiff line change Expand Up@@ -12,6 +12,6 @@ obj-$(CONFIG_XILINX_TSN_QBV) += xilinx_tsn_shaper.o obj-$(CONFIG_XILINX_TSN_QCI)+= xilinx_tsn_qci.o ...
8 changes: 4 additions & 4 deletions8drivers/net/ethernet/xilinx/xilinx_axienet_mcdma.c Original file line numberDiff line numberDiff line change Expand Up@@ -389,8 +389,8 @@ irqreturn_t __maybe_unused axienet_mcdma_tx_irq(int irq, void *_ndev) ...
(where a new packet can start in the same cycle that the current packet ends in) whenever the data is available to be combined from the same port. The packet parser/filtering logic works in single segment format and looks for an Ethernet type field at a fixed location within the pac...