VLSI implementation of DS-CDMA receiver using asynchronous designtechniquesOne of the most critical issues in designing electronics for\nportable equipment is keeping the power consumption low. This paper\ndesc
Asynchronousvs.SynchronousDesignTechniquesforNoCs RobertMullins “TheStatusoftheNetwork-on-ChipRevolution:DesignMethods,ArchitecturesandSiliconImplementation”,(Tutorial)InternationalSymposiumonSystem-on-Chip,Tampere,Finland.November14th,2005. AimsofTutorial
Mixed-timed circuits, clock domain crossing, GALS systems, Network-on-Chip, and multi-chip interconnects; Hardware implementations of asynchronous models and algorithms, asynchronous techniques in clocked designs, and elastic and latency-tolerant synchronous design; Circuit designs, case studies, comparisons...
and Frequency Scaling (DVFS) techniques which can be applied to this work for further reduction in power and also this architecture can be implemented in FPGA CONCLUSION A novel methodology for the design of globally-asynchronous, locally-synchronous systems called "synchro-tokens" has been presented...
exacerbates when large, multiple-clock domain designs are considered. In addition to the synchronization issues, the distribution of an asynchronous reset to millions of flip-flops is challenging, calling for techniques similar to CTS (Clock Tree Synthesis) and requiring similar area and routing ...
Top-Down Digital VLSI Design Book2015,Top-Down Digital VLSI Design Explore book No gating of reset signals Very much like a gated clock, we speak of agated resetwhen theasynchronous resetor preset input of a latch, flip-flop, register, counter, or some other state-preservingsubcircuitparticipat...
This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To...
low-power designFSM decompositionFSM partitioningasynchronous logicgated-clock techniquesRTL-synthesisPower consumption in a synchronous FSM (Finite-State Machine) can be reduced by partitioning it into a number of coupled sub-FSMs where only the part that is involved in a state transition is clocked...
SDM implementation is less sensitive to analog circuit imperfections due to reduced design complexity, oversampling and noise shaping techniques [2]. This inex- pensive system also meets the constraints like compact de- sign, minimum power, less noise and reduced conversion time. SDM performance can...
the cost of the system is often closely tied to the total area of the circuitry contained in the system. In such systems, a significant percentage of the area may be devoted to the instruction ROM of an embedded system, which stores the program code. Therefore, techniques to reduce the siz...