T. Nanya "Challenges to dependable Asynchronous Processor Design", Int\'l Symp. on Logic Synthesis and Microprocessor Architecture , pp.132 -139 1992T. Nanya, "Challenges to Dependable Asynchronous
embedded.com (July 28, 2017) Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of asynchronous reset and explore advanced solutions for ASIC vs FPGA designs....
Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-...
1. Asynchronous reset challenges A reset function is normally included in digital VLSI designs in order to bring the logic to a known state. Reset is mostly required for the control logic and may be eliminated from the data path logic, reducing logic area. Reset may be either synchronous or ...
Keywords: Asynchronous circuit, Sigma-Delta Modulator, Schmitt-Trigger, Tunable hysteresis, CMOS analog technology 1 Introduction With CMOS technology scaling, circuit implementation faces various challenges in integrating analog and mixed signal circuits. Reduced dimensions with low power, im- pacts ...
Neighbor discovery in traditional wireless networks and cognitive radio networks: Basics, taxonomy, challenges and future research directions 4.1.2 Asynchronous operation Pavlovska et al. (2010) proposed a rendezvous scheme for asynchronous operation based random ND protocol for CRNs in cooperative environ...
A solution to most digital data interface challenges would be to decouple the MCLK clock and the ODR clock domains. Therefore, ADI reintroduces the novel asynchronous sample rate conversion technique that enables the independence of the ODR clock and the data interface clock—thus breaking the age...
1. Asynchronous reset challenges A reset function is normally included in digital VLSI designs in order to bring the logic to a known state. Reset is mostly required for the control logic and may be eliminated from the data path logic, reducing logic area. Reset may be either synchronous or...
Some of the challenges described above, as well as others, may be addressed by apparatus, systems, and methods that operate to automatically synthesize synchronous logic that has been described by a hardware description language (HDL), or any high-level behavioral logic description, using automated...
turn, this causes additional challenges for planning the insertion of a conventional BIST because it must consider the clock domains for the memory to be tested as well as the physical locations of the memory within the layout of the device. Both result in increased design cycle time and ...