This paper presents a new hybrid 8-bit analog-to-digital convertor (ADC) combining a capacitive digital-to-analog (CDAC) based multi-bit/cycle successive approximation (SAR) ADC with a flash ADC. We extract 4 bits of MSB's from two rounds of 2-bit/cycle SAR operation and another 4 bits...
TONG X Y,CHEN J M,ZHU Z M,et al.A high performance 90nm CMOS SAR ADC with hybrid architecture[J].Journal of Semiconductors,2010,31(1):1-7.DOI:10.1088/1674-4926/31/1/015002.佟星元;陈剑鸣;朱樟明;杨银堂.A high performance 90 nm CMOS SAR ADC with hybrid architecture.半导体学报:英文版....
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[IEEE 2014 IEEE Custom Integrated Circuits Conference - CICC 2014 - San Jose, CA, USA (2014.9.15-2014.9.17)] Proceedings of the IEEE 2014 Custom Integrated Circuits Conference - A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping ...
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混合架构匹配性能纳米ADC非线性测量R型SAA 10-bit 2.5 MS/s SAR A/D converter is presented.In the circuit design,an R-C hybrid architecture D/A converter,pseudo-differential comparison architecture and low power voltage level shifters are utilized.Design challenges and considerations are also ...
A Hybrid Structure Noise Shaping SAR ADC doi:10.1142/S021812662550135XWorld Scientific Publishing CompanyJournal of Circuits, Systems and ComputersShengle RenXiangyu LiZhuqiang ShaoMeng GongMingyuan Ren
IEEE This paper presents a low-power and area efficient 10-bit SAR ADC with higher side-reset-and-set (HSRS) switching scheme and hybrid capacitive-MOS (CAP-MOS) DAC. The HSRS switching scheme consumes zero switching energy for the two most-significant bits and skips unnecessary switching wi...
was used in the wide band and very high-resolution applications of radar imaging, especially in SAR and ISAR [39]. This architecture results the fine resolution than the traditional beam scanning. Most recently, higher resolution can be achieved by this hybrid architecture with the dechirp ...
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