With a 10-bit SAR-ADC, if the reference voltage is used as 3-bit with a 6-bit capacitor array, the energy and area (number of capacitors) are reduced by 99.97 % and 93.75 %, respectively. Furthermore, we propose a switching algorithm that minimizes energy consumption, which is proven ...
This macro-cell is a general purpose, Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) subsystem. The DAC employs a hybrid architecture, using 6-bit resistive and 5-bit capacitive sub-DACs. It is a standard part, enabling...
混合架构匹配性能纳米ADC非线性测量R型SAA 10-bit 2.5 MS/s SAR A/D converter is presented.In the circuit design,an R-C hybrid architecture D/A converter,pseudo-differential comparison architecture and low power voltage level shifters are utilized.Design challenges and considerations are also ...
SAR-flash hybrid for energy-efficient high-speed conversion; SAR-assisted dual-residue pipelined ADC, which eliminates the stringent requirement for residue gain accuracy; and SAR-assisted delta–sigma modulator (DSM) with digital-domain noise coupling, which reduces the number of required anal...
Two hybrid, highly digital [equation]ADCs are presented in this work. A SAR+VCO 0-1 MASH architecture is used for a 12-bit scaling friendly ADC which does not require VCO nonlinearity correction...doi:10.1007/978-3-319-61285-0_4Arindam SanyalState...
A 0.49–4.34 μW LC-SAR Hybrid ADC with a 10.85-Bit ENOB and 20 KS/s Bandwidth by Hai Tang 1, Weilin Xu 1,*, Haiou Li 2, Baolin Wei 2 and Xueming Wei 2 1 Key Laboratory of Microelectronic Devices and Integrated Circuits, Education Department of Guangxi Zhuang Autonomous Region, Gu...
A Hybrid Structure Noise Shaping SAR ADC doi:10.1142/S021812662550135XWorld Scientific Publishing CompanyJournal of Circuits, Systems and ComputersShengle RenXiangyu LiZhuqiang ShaoMeng GongMingyuan Ren
IEEE This paper presents a low-power and area efficient 10-bit SAR ADC with higher side-reset-and-set (HSRS) switching scheme and hybrid capacitive-MOS (CAP-MOS) DAC. The HSRS switching scheme consumes zero switching energy for the two most-significant bits and skips unnecessary switching wi...
[IEEE 2014 IEEE Custom Integrated Circuits Conference - CICC 2014 - San Jose, CA, USA (2014.9.15-2014.9.17)] Proceedings of the IEEE 2014 Custom Integrated Circuits Conference - A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping ...
The ADC repeats the process until the completion of the (N − 1)th comparison is complete. The process is also called a loop bit. At the loop bit of the conversion process, the voltage on one side remains unchanged. The capacitor array switching energy for each comparison from the 3rd ...